1. Field of the Invention
The present invention relates to a semiconductor device having a function of detecting breakages (defect) of a semiconductor chip on a periphery of the semiconductor chip.
2. Related Art
When a semiconductor device is manufactured, by dicing a wafer having a predetermined circuit including a transistor formed thereon, individual pieces of semiconductor chips can be obtained. However, in the dicing, breakages such as chipping (uneven cut surface), a crack, and peeling of an interlayer insulating film may be caused on a periphery of the semiconductor chips. Conventionally, for detecting such breakages on the periphery of the semiconductor chips, visual inspection of the respective semiconductor chips after the dicing has been made using an optical microscope.
However, with an increase in wafer diameter and a decrease in chip size, it has become more and more difficult to carry out visual inspection on all the chips due to constraints in time. Further, even if breakages are caused on the periphery, there are cases where the breakage cannot be detected due to a limitation in resolution of the optical microscope.
As a countermeasure, Japanese Patent Application Laid-open Nos. Hei 7-193108, 2005-277338, and 2000-31230 disclose semiconductor chips whose breakage on a periphery caused after dicing can be electrically detected. In Japanese Patent Application Laid-open Nos. Hei 7-193108, 2005-277338, and 2000-31230, a conductive layer such as a wiring is provided on the periphery of the semiconductor chip. When a crack is caused on the periphery of the semiconductor chip, because the conductive layer is broken by the crack, the crack can be detected as an electrical characteristic.
For example, Japanese Patent Application Laid-open Nos. Hei 7-193108 and 2005-277338 each disclose a semiconductor device including a wiring having pads connected to both ends thereof and disposed along the periphery of the semiconductor chip, which can judge a quality of the semiconductor chip by reading a change in resistance between the pads.
More specifically, by reading the resistance of the wiring disposed along the periphery, breakages such as chipping of a semiconductor device can be finely detected. However, it is necessary to prepare pads and terminals for a package connected to the pads, and to prepare an external tester or the like for measuring the resistance between the pads, which increases a cost for an inspection of chipping and the like of the semiconductor device.
Further, Japanese Patent Application Laid-open No. 2000-31230 discloses a semiconductor device which includes a wiring disposed along the periphery of the semiconductor chip and which has a detection signal generating means connected to one end of the wiring (more specifically, the detection signal generating means is grounded) and an enable signal generating means connected to the other end of the wiring, for picking up a change in voltage when the semiconductor chip is chipped.
According to the semiconductor device described above, because the enable signal generating means is incorporated therein, no pad and tester for a test are necessary, which hardly increases the cost of the inspection of the semiconductor device. However, the enable signal generating means only binarily judges whether the wiring is connected or disconnected using a logic circuit. Therefore, it is impossible to appropriately set a threshold value for judging the quality, and there is a fear that, when the change in the resistance is minute, a non-defective product is erroneously judged as a defective product.
Meanwhile, in recent years, there is a case where interlayer insulating films of a semiconductor device are formed of different insulating materials in a lower layer portion and an upper layer portion. For example, the upper layer portion where a length of the wiring is relatively large and thus is liable to be influenced by parasitic capacitance is sometimes formed of an insulating material having a dielectric constant lower than that of the lower layer portion, such as a low dielectric constant material, in order to decrease the parasitic capacitance.
Peeling is more liable to occur at an interface between such interlayer insulating films formed of different insulating materials compared with an interface between interlayer insulating films formed of the same insulating material. Therefore, in a semiconductor device including a plurality of interlayer insulating films formed of different insulating materials, it is required to detect peeling caused by dicing at an interface between the interlayer insulating films with high accuracy.
In order to meet the requirement, Japanese Patent Application No. 2006-131610 filed by the same applicant as the present invention discloses a semiconductor device having a circuit forming region, the semiconductor device including a semiconductor substrate, a first interlayer insulating film formed on the semiconductor substrate and made of a first insulating material, a second interlayer insulating film formed on the first interlayer insulating film and made of a second insulating material different from the first insulating material, and a wiring structure disposed outside the circuit forming region and including a conductive plug, in which the wiring structure penetrates an interface between the first interlayer insulating film and the second interlayer insulating film.